From 7bc4dc5648c6ff37a847e99d7acee11e3e72a79d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 17 May 2018 18:40:32 +0530 Subject: soc/intel/common/block: Move tco common functions into block/smbus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc code into common/block/smbus. BUG=b:78109109 BRANCH=NONE TEST=Build and boot KBL/CNL/APL/ICL platform. Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8 Signed-off-by: Subrata Banik Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/26166 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/soc/intel/icelake/include/soc/smbus.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'src/soc/intel/icelake/include') diff --git a/src/soc/intel/icelake/include/soc/smbus.h b/src/soc/intel/icelake/include/soc/smbus.h index 64c3eb3f3a..f4f5b11288 100644 --- a/src/soc/intel/icelake/include/soc/smbus.h +++ b/src/soc/intel/icelake/include/soc/smbus.h @@ -16,11 +16,6 @@ #ifndef _SOC_ICELAKE_SMBUS_H_ #define _SOC_ICELAKE_SMBUS_H_ -/* PCI registers */ -#define TCOBASE 0x50 /* TCO base address. */ -#define TCOCTL 0x54 -#define TCO_BASE_EN (1 << 8) /* TCO base enable. */ - /* IO and MMIO registers under primary BAR */ /* Set address for PCH as SMBus slave role */ #define SMB_RCV_SLVA 0x09 @@ -29,10 +24,10 @@ #define TCO1_STS 0x04 #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) +#define TCO_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) /* * Default slave address value for PCH. This value is set to match default -- cgit v1.2.3