From c126084bc53e0f74f6085f4f84b5bc387d701a4f Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 23 Apr 2019 15:18:51 -0600 Subject: soc/intel: Add GPI interrupt config register offset info Add the offset information for GPI interrupt status and enable register in the pad_community structure. Populate the concerned information for individual SoCs. This offset information is required to clear the interrupt configuration during the bootup. BUG=b:130593883 BRANCH=None TEST=Ensure that the interrupt configuration are cleared during bootup. Ensured that the system boots to ChromeOS. Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/icelake/include/soc/gpio_defs.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel/icelake/include') diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 86d5fb2671..6ecda855d6 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -265,6 +265,8 @@ #define GPE_DW_SHIFT 8 #define GPE_DW_MASK 0xfff00 #define HOSTSW_OWN_REG_0 0xb0 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 #define PAD_CFG_BASE 0x600 -- cgit v1.2.3