From f538d74e9cf27d3353b3c1d56cb5be42c207ad84 Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Sun, 8 Dec 2019 11:04:09 +0100 Subject: vendorcode/intel: Remove Ice Lake FSP Bindings By updating the FSP submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. We are also adding back the CHANNEL_PRESENT enum, that is missing in the official headers. This was tested on the Razer Blade Stealth (late 2019). Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/37579 Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Christoph Pomaska Tested-by: build bot (Jenkins) --- src/soc/intel/icelake/Kconfig | 2 +- src/soc/intel/icelake/romstage/romstage.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/icelake') diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15e895fa1d..42e86c73b2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -180,7 +180,7 @@ config CBFS_SIZE config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/icelake/" + default "3rdparty/fsp/IceLakeFspBinPkg/Include" config FSP_FD_PATH string diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 7f1be731e8..37fc678cd9 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -35,6 +35,13 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +/* Memory Channel Present Status */ +enum { + CHANNEL_NOT_PRESENT, + CHANNEL_DISABLED, + CHANNEL_PRESENT +}; + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { -- cgit v1.2.3