From 512b77abb582e6c2566d3873b273dd32731e7bae Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamir.bohra@intel.com>
Date: Wed, 25 Mar 2020 13:20:34 +0530
Subject: soc/intel/jasperlake: Remove Tiger Lake SoC code from Jasper Lake

This is a follow-up patch to initial copy patch for Jasper Lake SoC.
Remove all Tiger Lake specfic code from Jasper Lake SoC code.

BUG=b:150217037

Change-Id: I44dc6bf55ca18a3f0c350f5c3e9fae2996958648
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39824
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/jasperlake/finalize.c | 6 ------
 1 file changed, 6 deletions(-)

(limited to 'src/soc/intel/jasperlake/finalize.c')

diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c
index b636ccbec0..714cda15e5 100644
--- a/src/soc/intel/jasperlake/finalize.c
+++ b/src/soc/intel/jasperlake/finalize.c
@@ -12,12 +12,6 @@
  * GNU General Public License for more details.
  */
 
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 4, 29
- */
-
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <bootstate.h>
-- 
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