From b17f3d3d3cdd215edcff492699c744a4c85908d0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 24 Oct 2019 00:19:45 +0200 Subject: soc,mb/intel: clean up remaining FSP2.0 socs/boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove CONFIG_...FSP2.0 based if-switches from FSP2.0-only socs/boards Change-Id: Iae92dc2e2328b14c78ac686aaf326bd68430933b Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/36279 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/quark/fsp_params.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 src/soc/intel/quark/fsp_params.c (limited to 'src/soc/intel/quark/fsp_params.c') diff --git a/src/soc/intel/quark/fsp_params.c b/src/soc/intel/quark/fsp_params.c new file mode 100644 index 0000000000..d96d410f9a --- /dev/null +++ b/src/soc/intel/quark/fsp_params.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) +{ +} + +asmlinkage void chipset_teardown_car(void) +{ +} -- cgit v1.2.3