From 43cdff6b453e0563414a020c2bab69a841a8f2e8 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 7 Feb 2016 14:52:22 -0800 Subject: soc/intel/quark: MTRR support Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select DISPLAY_MTRRS" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13530 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG --- src/soc/intel/quark/include/soc/pci_devs.h | 6 ++++++ src/soc/intel/quark/include/soc/romstage.h | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'src/soc/intel/quark/include') diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 0543a05b53..4ab23b9745 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,6 +18,12 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ +#include +#include + +/* DEVICE 0 (Memroy Controller Hub) */ +#define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) + /* IO Fabric 1 */ #define SIO1_DEV 0x14 # define HSUART1_DEV SIO1_DEV diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index a35f4a6dd2..3a1320cafc 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,8 +22,14 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif +#include #include +#include +void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); +uint32_t mdr_read(void); +void mdr_write(uint32_t value); +void mea_write(uint32_t reg_address); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); #endif /* _QUARK_ROMSTAGE_H_ */ -- cgit v1.2.3