From 87df8d08d676f79b894da84ebe6f8a57f69ba5b1 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 7 Feb 2016 14:37:13 -0800 Subject: soc/intel/quark: Enable Serial Port Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13445 Tested-by: build bot (Jenkins) Reviewed-by: FEI WANG --- src/soc/intel/quark/romstage/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/quark/romstage/Makefile.inc') diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index cb17d3d155..6ade32de69 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -15,3 +15,6 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +romstage-y += romstage.c +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c -- cgit v1.2.3