From 6ea6775fa3eaa78b5322833940b9ba32d784556b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 27 May 2018 14:37:52 +0200 Subject: soc/{amd,intel}: Use postcar_frame_add_romcache() Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/26580 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/quark/romstage/fsp2_0.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/soc/intel/quark') diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 74796448c4..900ec1b4ca 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -80,8 +80,7 @@ asmlinkage void *car_stage_c_entry(void) postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); /* Cache SPI flash - Write protect not supported */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRTHROUGH); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); run_postcar_phase(&pcf); return NULL; -- cgit v1.2.3