From 91bc620702bf18c5dcbeb9f4f4a91305398b16f4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 18 Aug 2019 05:07:47 +0300 Subject: intel/quark: Use common romstage entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ifb2adcdef7265d43cb2bf6886f126f1a17bf08a0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35146 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/fsp2_0.c | 8 +------- 2 files changed, 2 insertions(+), 7 deletions(-) (limited to 'src/soc/intel/quark') diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index be5b320351..13963d4b23 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -22,5 +22,6 @@ romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c postcar-y += mtrr.c diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index b3f3ee8cb6..6e23de7039 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include #include #include #include @@ -28,9 +27,7 @@ #include #include -static struct postcar_frame early_mtrrs; - -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { bool s3wake; @@ -61,9 +58,6 @@ asmlinkage void car_stage_entry(void) /* Initialize the PCIe bridges */ pcie_init(); - - prepare_and_run_postcar(&early_mtrrs); - /* We do not return here. */ } static struct chipset_power_state power_state; -- cgit v1.2.3