From a2d4062d427d18127707306dada5e79d69bd3691 Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Tue, 30 Aug 2016 20:47:13 +0530 Subject: soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi Signed-off-by: Naresh G Solanki Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/skylake/Kconfig | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/Kconfig') diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db31ee..9d649d23a6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -35,14 +35,12 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE - select PLATFORM_USES_FSP1_1 select REG_SCRIPT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET @@ -54,6 +52,24 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC +choice + prompt "FSP Driver" + default USE_FSP1_1_DRIVER + +config USE_FSP2_0_DRIVER + bool "Build with FSP 2.0" + select PLATFORM_USES_FSP2_0 + select ADD_VBT_DATA_FILE + select SOC_INTEL_COMMON_GFX_OPREGION + +config USE_FSP1_1_DRIVER + bool "Build with FSP 1.1" + select PLATFORM_USES_FSP1_1 + select GOP_SUPPORT + select DISPLAY_FSP_ENTRY_POINTS + +endchoice + config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC -- cgit v1.2.3