From e4a8537ce20d801a5985ba6268ae83593063a4bf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 24 Jul 2016 00:36:12 +0530 Subject: soc/intel/skylake: Add C entry bootblock support List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Rizwan Qureshi Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Kconfig | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) (limited to 'src/soc/intel/skylake/Kconfig') diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 5f12f5bb4a..bbffd17f6d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select ACPI_NHLT + select BOOTBLOCK_CONSOLE select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select C_ENVIRONMENT_BOOTBLOCK @@ -61,22 +62,10 @@ config CHROMEOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH select VIRTUAL_DEV_SWITCH -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/skylake/bootblock/cpu.c" - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "soc/intel/skylake/bootblock/systemagent.c" - config BOOTBLOCK_RESETS string default "soc/intel/common/reset.c" -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "soc/intel/skylake/bootblock/pch.c" - config CBFS_SIZE hex default 0x200000 -- cgit v1.2.3