From 1d14b3e926c15027f9272f1e80b8913fef8cf25d Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Tue, 12 May 2015 18:23:27 -0700 Subject: soc/intel: Add Skylake SOC support Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Makefile.inc | 108 +++++++++++++++---------------------- 1 file changed, 42 insertions(+), 66 deletions(-) (limited to 'src/soc/intel/skylake/Makefile.inc') diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index dafceb7e22..af299c3c74 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -3,81 +3,78 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y) subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage +subdirs-y += ../common +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -ramstage-y += acpi.c -ramstage-y += adsp.c +romstage-y += gpio.c +romstage-y += memmap.c +romstage-y += pch.c +romstage-y += pcr.c +romstage-y += pei_data.c +romstage-y += pmutil.c +romstage-y += smbus_common.c +romstage-y += tsc_freq.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += cpu_info.c -smm-y += cpu_info.c -ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += elog.c ramstage-y += finalize.c +ramstage-y += flash_controller.c ramstage-y += gpio.c -romstage-y += gpio.c -smm-y += gpio.c -ramstage-y += hda.c ramstage-y += igd.c -ramstage-y += iobp.c -romstage-y += iobp.c ramstage-y += lpc.c -ramstage-y += me.c -ramstage-y += me_status.c -romstage-y += me_status.c ramstage-y += memmap.c -romstage-y += memmap.c -ramstage-y += minihd.c ramstage-y += monotonic_timer.c -smm-y += monotonic_timer.c ramstage-y += pch.c -romstage-y += pch.c ramstage-y += pcie.c +ramstage-y += pcr.c ramstage-y += pei_data.c -romstage-y += pei_data.c +ramstage-y += pmc.c ramstage-y += pmutil.c -romstage-y += pmutil.c -smm-y += pmutil.c ramstage-y += ramstage.c -ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += reset.c -romstage-y += reset.c -ramstage-y += sata.c -ramstage-y += serialio.c ramstage-y += smbus.c ramstage-y += smbus_common.c -romstage-y += smbus_common.c ramstage-y += smi.c -smm-y += smihandler.c ramstage-y += smmrelocate.c -ramstage-y += spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -ramstage-y += stage_cache.c -romstage-y += stage_cache.c ramstage-y += systemagent.c ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-y += tsc_freq.c -ramstage-y += ehci.c +ramstage-y += uart.c ramstage-y += xhci.c -smm-y += xhci.c -ifeq ($(CONFIG_USBDEBUG),y) -ramstage-y += usbdebug.c -romstage-y += usbdebug.c -smm-y += usbdebug.c -endif +smm-y += cpu_info.c +smm-y += gpio.c +smm-y += monotonic_timer.c +smm-y += pcr.c +smm-y += pch.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c +smm-y += tsc_freq.c + +CPPFLAGS_common += -I$(src)/arch/x86/include/ +CPPFLAGS_common += -I$(src)/soc/intel/skylake +CPPFLAGS_common += -I$(src)/soc/intel/skylake/include -CPPFLAGS_common += -Isrc/soc/intel/broadwell/include +CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR) + +CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1 +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1 +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4 +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32 +CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH) # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS -INTERMEDIATE := broadwell_add_me +INTERMEDIATE := pch_add_me ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin @@ -88,7 +85,7 @@ else IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) endif -broadwell_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) +pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf "\n** WARNING **\n" printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" @@ -106,29 +103,8 @@ ifeq ($(CONFIG_HAVE_ME_BIN),y) -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) - printf " IFDTOOL Locking Management Engine\n" - $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre -else - printf " IFDTOOL Unlocking Management Engine\n" - $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre - mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif -endif - -PHONY += broadwell_add_me - -# If an MRC file is an ELF file determine the entry address and first loadable -# section offset in the file. Subtract the offset from the entry address to -# determine the final location. -mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' ) -mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }') -# Add memory reference code blob. -cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin -mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) -mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) -mrc.bin-type := mrc +PHONY += pch_add_me endif -- cgit v1.2.3