From 68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 18 Jul 2016 14:13:52 +0530 Subject: soc/intel/skylake: Do cache as ram and prepare for C entry Enable cache-as-ram and prepare for c entry in bootblock. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x2A Credits-to: Aaron Durbin Signed-off-by: Barnali Sarkar Signed-off-by: Rizwan Qureshi Signed-off-by: Subrata Banik Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1 Reviewed-on: https://review.coreboot.org/15784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/skylake/Makefile.inc') diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 3928b97d03..30ff7b79de 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -9,6 +9,9 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/cache_as_ram.S + verstage-y += gpio.c verstage-y += memmap.c verstage-y += monotonic_timer.c -- cgit v1.2.3