From cb8849b68671c54ea2521cd8fb1ba289136b5b85 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 4 Nov 2016 13:26:41 +0530 Subject: soc/intel/skylake: Fix SATA booting to OS issue SATA device remains unrecognized if connected at Port 2. Port control and Status register (PCS) is by default set by hardware to the disabled state as a result of an initial power on reset. OS read PCS register during boot causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/17229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/skylake/Makefile.inc') diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 32eb708a97..f02f9561e2 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -73,6 +73,7 @@ ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += sata.c ramstage-y += sd.c ramstage-y += smbus.c ramstage-y += smbus_common.c -- cgit v1.2.3