From 7837c203d615fce03c6d89d99ba9a746619e49d4 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 7 May 2018 17:13:40 +0530 Subject: soc/intel/common/block: Move p2sb common functions into block/p2sb This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/p2sb. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/26132 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/bootblock/pch.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) (limited to 'src/soc/intel/skylake/bootblock') diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index ef61a60291..4c88ed55bf 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -22,9 +22,10 @@ #include #include #include +#include #include -#include #include +#include #include #include #include @@ -44,29 +45,11 @@ #define PCR_DMI_PMBASEC 0x27B0 #define PCR_DMI_TCOBASE 0x2778 -static void enable_p2sbbar(void) -{ - pci_devfn_t dev = PCH_DEV_P2SB; - - /* Enable PCR Base address in PCH */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); - - /* Enable P2SB MSE */ - pci_write_config8(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - /* - * Enable decoding for HPET memory address range. - * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode - * the High Performance Timer memory address range - * selected by bits 1:0 - */ - pci_write_config8(dev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT); -} - void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); - enable_p2sbbar(); + p2sb_enable_bar(); + p2sb_configure_hpet(); } static void soc_config_acpibase(void) -- cgit v1.2.3