From bffff54e09e3fb91f94bd126814aaf1c200fa96b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 9 Nov 2017 15:07:44 +0530 Subject: soc/intel/skylake: Make use of common CSE code for skylake TEST=Ensures global reset could able to reset system. Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/22395 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/bootblock/pch.c | 25 +++---------------------- 1 file changed, 3 insertions(+), 22 deletions(-) (limited to 'src/soc/intel/skylake/bootblock') diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index fdc88f5641..34cfaa34e8 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -157,27 +158,6 @@ static void soc_config_tco(void) outw(tcocnt, tcobase + TCO1_CNT); } -static void enable_heci(void) -{ - device_t dev = PCH_DEV_CSE; - u8 pcireg; - - /* Assign Resources to HECI1 */ - /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for HECI1 */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); -} - void pch_early_iorange_init(void) { /* IO Decode Range */ @@ -216,5 +196,6 @@ void pch_early_init(void) enable_rtc_upper_bank(); - enable_heci(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); } -- cgit v1.2.3