From a2d4062d427d18127707306dada5e79d69bd3691 Mon Sep 17 00:00:00 2001 From: Naresh G Solanki Date: Tue, 30 Aug 2016 20:47:13 +0530 Subject: soc/intel/skylake: Add FSP 2.0 support in ramstage Add FSP 2.0 support in ramstage. Populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for pre OS screens. Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497 Signed-off-by: Rizwan Qureshi Signed-off-by: Naresh G Solanki Reviewed-on: https://review.coreboot.org/16592 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/soc/intel/skylake/chip.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/soc/intel/skylake/chip.h') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 62e28e693c..00393b2492 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -273,6 +273,19 @@ struct soc_intel_skylake_config { u16 PchConfigSubSystemVendorId; /* Subsystem ID of the PCH devices*/ u16 PchConfigSubSystemId; + + /* + * Determine if WLAN wake from Sx, corresponds to the + * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanEnable; + + /* + * Determine if WLAN wake from DeepSx, corresponds to + * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanDeepSxEnable; + /* * Corresponds to the "WOL Enable Override" bit in the General PM * Configuration B (GEN_PMCON_B) register -- cgit v1.2.3