From d0def394133024bea50a3b89b1d0ff579a3cc011 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 22 Jul 2015 12:19:28 +0530 Subject: intel/skylake: IRQ programming through UPD Implemented Device IRQ porgramming, PxRC to IRQ mapping, GPIO IRQ routing, SCI IRQ select through UPD BUG=NONE BRANCH=NONE CQ-DEPEND=CL:*232948 TEST= build and booted sklrvp,kunimitsu with this changes. Change-Id: Ic98074491fe5251a48ed55b6fb7ef31809c3abf3 Signed-off-by: Patrick Georgi Original-Commit-Id: 534bd65e5df8654d745c8efe491a332336c9cdc3 Original-Change-Id: I4ea6f3cdb15d371c6023bfd046f3475290f5aa26 Original-Signed-off-by: Subrata Banik Original-Signed-off-by: Rizwan Qureshi Original-Reviewed-on: https://chromium-review.googlesource.com/291403 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/12146 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/chip.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/skylake/chip.h') diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index dd5306e078..b54869c051 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -238,6 +238,13 @@ struct soc_intel_skylake_config { u32 GraphicsConfigPtr; u8 Device4Enable; u8 RtcLock; + /* GPIO IRQ Route The valid values is 14 or 15*/ + u8 GpioIrqSelect; + /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ + u8 SciIrqSelect; + /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/ + u8 TcoIrqSelect; + u8 TcoIrqEnable; }; typedef struct soc_intel_skylake_config config_t; -- cgit v1.2.3