From 48f96739edbe8d532e0d74c32e11fe422d44e02c Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 17 Jul 2017 16:45:54 +0530 Subject: soc/intel/skylake: Remove Heci2 and Heci3 from wake resource list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit HECI2 and HECI3 devices are “function disable” during FSP Silicon Init phase. Device will not be visible over PCI bus hence removing these devices from wake source list. Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/20613 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/elog.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/intel/skylake/elog.c') diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index fde8be2f7d..1178e80ff8 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -216,8 +216,6 @@ static void pch_log_pme_internal_wake_source(void) { PCH_DEVFN_PCIE12, 0xa4, ELOG_WAKE_SOURCE_PME_PCIE12 }, { PCH_DEVFN_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA }, { PCH_DEVFN_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE }, - { PCH_DEVFN_CSE_2, 0x54, ELOG_WAKE_SOURCE_PME_CSE2 }, - { PCH_DEVFN_CSE_3, 0x54, ELOG_WAKE_SOURCE_PME_CSE3 }, { PCH_DEVFN_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI }, { PCH_DEVFN_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI }, }; -- cgit v1.2.3