From 9a016236d4d67e0c95245d0e67ab85ba2a242359 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 14 Aug 2019 12:10:48 +0200 Subject: soc/intel/skylake/vr_config: Add loadline defaults MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In addition to zero IccMax specified by mainboard with socketed CPU, allow a zero LoadLine default. The SoC code will fill in the default AC/DC LoadLine values are per datasheets: * "7th Generation Intel® Processor Families for H Platforms, Vol 1" Document Number: 335190-003 * "7th Generation Intel® Processor Families for S Platforms and Intel ®Core™ X-Series Processor Family, Vol 1" Document Number: 335195-003 The AC/DC LoadLine is CPU and board specific. TODO: Find out how to get the LoadLine from vendor firmware and find out how to map those to different CPU LoadLines. Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/34938 Reviewed-by: Philipp Deppenwiese Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/include/soc/vr_config.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 465e248700..aebbbdff4a 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -68,6 +68,7 @@ struct vr_config { }; #define VR_CFG_AMP(i) ((i) * 4) +#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) #if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains -- cgit v1.2.3