From d3476809955ffb69447cc02a5ea893ebd1da3eb3 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Sat, 8 Jul 2017 01:08:40 -0700 Subject: soc/intel/skylake: Add support in SKL for PMC common code Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/20499 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/include/soc/gpe.h | 2 ++ src/soc/intel/skylake/include/soc/pm.h | 47 ++++++++++++--------------------- src/soc/intel/skylake/include/soc/pmc.h | 6 ++--- 3 files changed, 21 insertions(+), 34 deletions(-) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/gpe.h b/src/soc/intel/skylake/include/soc/gpe.h index 655cc1127b..d0962b84d8 100644 --- a/src/soc/intel/skylake/include/soc/gpe.h +++ b/src/soc/intel/skylake/include/soc/gpe.h @@ -130,4 +130,6 @@ #define GPE0_LAN_WAK 112 #define GPE0_WADT 114 +#define GPE_MAX GPE0_WADT + #endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index a547094c37..00578180eb 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include /* ACPI_BASE_ADDRESS / PMBASE */ @@ -103,6 +105,7 @@ #define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */ #define GPE_95_64 2 /* 0x88/0x98 = GPE[95:64] */ #define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD #define WADT_STS (1 << 18) #define LAN_WAK_STS (1 << 16) #define GPIO_T2_STS (1 << 15) @@ -136,6 +139,13 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 +/* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ +#define ETR 0xac +# define CF9_LOCK (1 << 31) +# define CF9_GLB_RST (1 << 20) + +#define PRSTS 0x10 + struct chipset_power_state { uint16_t pm1_sts; uint16_t pm1_en; @@ -150,49 +160,26 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __packed; +/* + * This is used only in FSP1_1 as we wanted to keep the flow unchanged. + * Internally fill_power_state calls the new pmc_fill_power_state now + */ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) struct chipset_power_state *fill_power_state(void); - -/* PM1_CNT */ -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); - -/* PM1 */ -uint16_t clear_pm1_status(void); -void enable_pm1(uint16_t events); -void update_pm1_enable(uint16_t events); -uint16_t read_pm1_enable(void); -uint32_t clear_smi_status(void); - -/* SMI */ -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); - -/* TCO */ -uint32_t clear_tco_status(void); -void enable_tco_sci(void); - -/* GPE0 */ -uint32_t clear_gpe_status(void); -void clear_gpe_enable(void); -void enable_all_gpe(uint32_t set1, uint32_t set2, uint32_t set3, uint32_t set4); -void disable_all_gpe(void); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); +#endif /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void); /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); + /* Get base address of TCO I/O registers. */ uint16_t smbus_tco_regs(void); /* Set the DISB after DRAM init */ void pmc_set_disb(void); -/* Initialize GPEs */ -void pmc_gpe_init(void); - /* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index 4a80917fe4..bd86f95e38 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -91,11 +91,9 @@ #define DSX_EN_LAN_WAKE_PIN (1 << 0) #define PMSYNC_TPR_CFG 0xc4 #define PMSYNC_LOCK (1 << 31) -#define GPIO_CFG 0x120 +#define GPIO_GPE_CFG 0x120 #define GPE0_DWX_MASK 0xf -#define GPE0_DW0_SHIFT 0 -#define GPE0_DW1_SHIFT 4 -#define GPE0_DW2_SHIFT 8 +#define GPE0_DW_SHIFT(x) (4*(x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 #define CIR31C 0x31c -- cgit v1.2.3