From e33a1724b34d839fae16836a5bdde4d53a788c15 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 30 Jul 2015 16:52:56 -0500 Subject: skylake: fix serial port with new code base Many Kconfig options changed in coreboot.org since skylake was first started. Fix Kconfig option name changes, and also provide a common option, UART_DEBUG that can be selected to select all the necessary options. Note: It's still a requirement to manually unset the 8250IO option because that's unconditionally set. BUG=chrome-os-partner:43419 BUG=chrome-os-partner:43463 BRANCH=None TEST=Built glados. Booted into kernel. Kernel reboots somewhere. Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/289951 Original-Reviewed-by: Duncan Laurie Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11172 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/include/soc/iomap.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index c478dafead..764e9665e2 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -27,6 +27,9 @@ #define PCH_PCR_BASE_ADDRESS 0xfd000000 #define PCH_BCR_BASE_SIZE 0x1000000 +#define UART_DEBUG_BASE_ADDRESS 0xfe034000 +#define UART_DEBUG_BASE_SIZE 0x1000 + #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000 -- cgit v1.2.3