From f45eb062da5a78425d52732b0a0a988b30457c24 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 17 Sep 2015 11:50:39 -0700 Subject: skylake: SPI code cleanup Move base address into iomap.h. Use PCI symbols instead of SPI specific symbols. Fix comments. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/11826 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/include/soc/iomap.h | 2 ++ src/soc/intel/skylake/include/soc/spi.h | 7 +------ 2 files changed, 3 insertions(+), 6 deletions(-) (limited to 'src/soc/intel/skylake/include') diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 333906b348..7dea6ae011 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -53,6 +53,8 @@ #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 +#define SPI_BASE_ADDRESS 0xfe010000 + #define GPIO_BASE_SIZE 0x10000 /* diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h index a31c9b2ceb..cf55e9de05 100644 --- a/src/soc/intel/skylake/include/soc/spi.h +++ b/src/soc/intel/skylake/include/soc/spi.h @@ -26,12 +26,7 @@ * should support most common flash chips. */ #define SPIDVID_OFFSET 0x0 -/* Temporay SPI BASE ADDRESS */ -#define TEMP_SPI_BAR 0xFE010000 -/* SPI BASE ADDRESS Register */ -#define B_PCH_SPI_BAR0_MASK 0x0FFF -#define PCH_SPI_BASE_ADDRESS 0x10 -#define SPIBAR_MEMBAR_MASK 0xFFFFF000 + /* Reigsters within the SPIBAR */ #define SPIBAR_SSFC 0xA1 -- cgit v1.2.3