From 66318aad07e6810065bc0668f4a1f34b7cb77687 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 4 May 2019 16:59:20 +0200 Subject: intel/fsp1_1: Move MRC cache pointers into `romstage_params` These are part of a common concept and not SoC specific. Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Patrick Rudolph Reviewed-by: Frans Hendriks --- src/soc/intel/skylake/romstage/romstage.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/soc/intel/skylake/romstage/romstage.c') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 0501b04493..8ec08c2d0f 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -46,6 +46,12 @@ void soc_pre_ram_init(struct romstage_params *params) /* Prepare to initialize memory */ soc_fill_pei_data(params->pei_data); + + const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *const config = + dev ? dev->chip_info : NULL; + /* Force a full memory train if RMT is enabled */ + params->disable_saved_data = config && config->Rmt; } /* UPD parameters to be initialized before MemoryInit */ -- cgit v1.2.3