From d5f645c6cde230004ee5af6c62d451d1329928e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 28 Sep 2019 00:20:27 +0300 Subject: soc/intel: Replace config_of_path() with config_of_soc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/romstage/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/skylake/romstage/romstage.c') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index a8bbfb633d..f354af3442 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -43,7 +43,7 @@ void soc_pre_ram_init(struct romstage_params *params) /* Program MCHBAR and DMIBAR */ systemagent_early_init(); - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* Force a full memory train if RMT is enabled */ params->disable_saved_data = config->Rmt; @@ -57,7 +57,7 @@ void soc_memory_init_params(struct romstage_params *params, /* Set the parameters for MemoryInit */ - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* * Set IGD stolen size to 64MB. The FBC hardware for skylake does not -- cgit v1.2.3