From e4a8537ce20d801a5985ba6268ae83593063a4bf Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 24 Jul 2016 00:36:12 +0530 Subject: soc/intel/skylake: Add C entry bootblock support List of activity performing in this patch - early PCH programming - early SA programming - early CPU programming - mainborad early gpio programming for UART and SPI - car setup - move chipset programming from verstage to post console BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and booted kunimitsu till POST code 0x34 Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143 Signed-off-by: Barnali Sarkar Signed-off-by: Naveen Krishna Chatradhi Signed-off-by: Rizwan Qureshi Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/15785 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/romstage/romstage.c | 18 ------------------ 1 file changed, 18 deletions(-) (limited to 'src/soc/intel/skylake/romstage/romstage.c') diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index b16e5aa22c..56a5a92255 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -49,24 +49,6 @@ void soc_pre_ram_init(struct romstage_params *params) soc_fill_pei_data(params->pei_data); } -/* SOC initialization before the console is enabled. */ -void car_soc_pre_console_init(void) -{ - /* System Agent Early Initialization */ - systemagent_early_init(); - - if (IS_ENABLED(CONFIG_UART_DEBUG)) - pch_uart_init(); -} - -void car_soc_post_console_init(void) -{ - report_platform_info(); - set_max_freq(); - pch_early_init(); - i2c_early_init(); -} - int get_sw_write_protect_state(void) { u8 status; -- cgit v1.2.3