From 42cfdf5184b3e94805958a3368f2e049c09119ac Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 21 Dec 2016 10:58:26 -0800 Subject: soc/intel/skylake: Use the new SPI driver interface 1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCh=None TEST=Compiles successfully for chell and eve. Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/17933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/romstage/spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/skylake/romstage') diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c index 16224046d7..41e06a7933 100644 --- a/src/soc/intel/skylake/romstage/spi.c +++ b/src/soc/intel/skylake/romstage/spi.c @@ -27,7 +27,7 @@ int early_spi_read_wpsr(u8 *sr) uint8_t rdsr; int ret = 0; - spi_init(); + spi_flash_init(); /* sending NULL for spiflash struct parameter since we are not * calling HWSEQ read_status() call via Probe. -- cgit v1.2.3