From 1d14b3e926c15027f9272f1e80b8913fef8cf25d Mon Sep 17 00:00:00 2001
From: Lee Leahy <leroy.p.leahy@intel.com>
Date: Tue, 12 May 2015 18:23:27 -0700
Subject: soc/intel: Add Skylake SOC support

Add the files to support the Skylake SOC.
Matches chromium tree at 927026db

BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform

Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/intel/skylake/uart.c | 76 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 src/soc/intel/skylake/uart.c

(limited to 'src/soc/intel/skylake/uart.c')

diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c
new file mode 100644
index 0000000000..36b1b5a71b
--- /dev/null
+++ b/src/soc/intel/skylake/uart.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <console/uart.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+
+static int pch_uart_is_debug(struct device *dev)
+{
+	if (!IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE))
+		return 0;
+
+	switch (dev->path.pci.devfn) {
+	case PCH_DEVFN_UART0:
+		return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0;
+	case PCH_DEVFN_UART1:
+		return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1;
+	case PCH_DEVFN_UART2:
+		return CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 2;
+	}
+	return 0;
+}
+
+static void pch_uart_read_resources(struct device *dev)
+{
+	pci_dev_read_resources(dev);
+
+	/* Set the configured UART base address for the debug port */
+	if (pch_uart_is_debug(dev)) {
+		struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+		res->size = 0x1000;
+		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+			IORESOURCE_FIXED;
+	}
+}
+
+static struct device_operations device_ops = {
+	.read_resources		= &pch_uart_read_resources,
+	.set_resources		= &pci_dev_set_resources,
+	.enable_resources	= &pci_dev_enable_resources,
+	.ops_pci		= &soc_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = {
+	0x9d27, /* UART0 */
+	0x9d28, /* UART1 */
+	0x9d66, /* UART2 */
+	0
+};
+
+static const struct pci_driver pch_uart __pci_driver = {
+	.ops	 = &device_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
-- 
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