From 223ddc298a1a8e25a493987d84c629ed152821d1 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Tue, 12 Feb 2019 21:14:13 +0800 Subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors. BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen Reviewed-on: https://review.coreboot.org/c/31368 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/gpio.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index f67d4a3bb9..4da705da73 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -168,3 +168,18 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) *num = ARRAY_SIZE(routes); return routes; } + +uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, + int dw_reg, uint32_t reg_val) +{ + if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + return reg_val; + /* + * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 + * ~ GPP_F11. + */ + if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1) + reg_val = reg_val & ~(PAD_CFG1_TOL_1V8); + return reg_val; + +} -- cgit v1.2.3