From 6267cc523b4a6f716060214d06a8226412a65837 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 15 Oct 2020 00:07:44 +0200 Subject: soc/intel: drop unneeded ISST configuration code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The code configuring ISST (Intel SpeedShift Technology) sets the ISST capability bits in CPUID.06H:EAX. It does *not* activate HWP (Hardware P-States), which shall be done by the OS only. Since the capability is enabled by default (opt-out), there is nothing to do for us in the enabled-case. Practically speaking, there is no value at all in disabling the capability, since one can configure the OS to not enable HWP if that is desired. The two other bits for EPP and HWP interrupt that were set by the code are not set anymore, too. It was tested, on three platforms so far (CML-U, KBL-H, SKL-U), that these are set as well by default in the MSRs reset value (0x1cc0). To reduce complexity and duplicated code without actual benefit, this code gets dropped. The remaining dt option will be dropped in CB:46462. Test: Linux on Supermicro X11SSM-F detects and enables HWP: [ 0.415017] intel_pstate: HWP enabled Change-Id: I952720cf1de78b00b1bf749f10e9c0acd6ecb6b7 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46460 Reviewed-by: Nico Huber Reviewed-by: Tim Wawrzynczak Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/cpu.c | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index fcec0cefba..1682503d4b 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -27,31 +27,6 @@ #include "chip.h" -static void configure_isst(void) -{ - config_t *conf = config_of_soc(); - msr_t msr; - - if (conf->speed_shift_enable) { - /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - * is supported or not. coreboot needs to configure MSR 0x1AA - * which is then reflected in the CPUID register. - */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ - msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } else { - msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ - msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ - wrmsr(MSR_MISC_PWR_MGMT, msr); - } -} - static void configure_misc(void) { config_t *conf = config_of_soc(); @@ -163,9 +138,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Configure Intel Speed Shift */ - configure_isst(); - set_aesni_lock(); /* Enable ACPI Timer Emulation via MSR 0x121 */ -- cgit v1.2.3