From 71756c21afd14f4114c597487406eb53e23730b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 12 Jul 2019 13:10:19 +0300 Subject: soc/intel: Expand SA_DEV_ROOT for ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/include/soc/pci_devs.h | 16 ++++------------ src/soc/intel/skylake/romstage/romstage_fsp20.c | 6 +++--- src/soc/intel/skylake/smmrelocate.c | 3 ++- src/soc/intel/skylake/systemagent.c | 5 +++-- src/soc/intel/skylake/vr_config.c | 6 ++++-- 5 files changed, 16 insertions(+), 20 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 0669ced18c..7147876e9c 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -19,34 +19,26 @@ #include -#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if !defined(__SIMPLE_DEVICE__) #include -#define _SA_DEV(slot) pcidev_path_on_root_debug(_SA_DEVFN(slot), __func__) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else -#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) -#define SA_DEV_ROOT _SA_DEV(ROOT) +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #define SA_DEV_SLOT_PEG 0x01 -#define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) -#define SA_DEV_PEG(func) pcidev_path_on_root_debug(SA_DEVFN_PEG(func), __func__) -#define SA_DEV_PEG0 SA_DEV_PEG(0) -#define SA_DEV_PEG1 SA_DEV_PEG(1) -#define SA_DEV_PEG2 SA_DEV_PEG(2) #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEVFN_IGD _SA_DEVFN(IGD) -#define SA_DEV_IGD _SA_DEV(IGD) +#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) +#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) /* PCH Devices */ diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index b15fa89292..bb86c6300d 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -223,7 +223,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, * If PEG port is not defined in the device tree, it will be disabled * in FSP */ - dev = SA_DEV_PEG0; /* PEG 0:1:0 */ + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */ if (!dev || !dev->enabled) m_cfg->Peg0Enable = 0; else if (dev->enabled) { @@ -238,7 +238,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, m_t_cfg->Peg0Gen3EqPh3Method = 0; } - dev = SA_DEV_PEG1; /* PEG 0:1:1 */ + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */ if (!dev || !dev->enabled) m_cfg->Peg1Enable = 0; else if (dev->enabled) { @@ -250,7 +250,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, m_t_cfg->Peg1Gen3EqPh3Method = 0; } - dev = SA_DEV_PEG2; /* PEG 0:1:2 */ + dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */ if (!dev || !dev->enabled) m_cfg->Peg2Enable = 0; else if (dev->enabled) { diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 72861874c9..816e1a8963 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -310,11 +310,12 @@ void smm_relocate(void) void smm_lock(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can * make the SMM registers writable again. */ printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); + pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index ea5526264b..410265f68e 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -29,7 +29,7 @@ bool soc_is_vtd_capable(void) { - struct device *const root_dev = SA_DEV_ROOT; + struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); return root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); } @@ -42,7 +42,8 @@ bool soc_is_vtd_capable(void) */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { - struct device *const igd_dev = SA_DEV_IGD; + struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, "PCIEXBAR" }, diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 905154e8ac..c83e18dd1d 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -174,17 +174,19 @@ static uint16_t get_dev_id(struct device *dev) static int get_kbl_sku(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); static int sku = -1; uint16_t id; if (sku != -1) return sku; - id = get_dev_id(SA_DEV_ROOT); + id = get_dev_id(sa_dev); if (id == PCI_DEVICE_ID_INTEL_KBL_U_R) sku = KBL_R_SKU; else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) { - id = get_dev_id(SA_DEV_IGD); + struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + id = get_dev_id(igd_dev); if (id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) sku = AML_Y_SKU; else -- cgit v1.2.3