From cc35f723fdcc6999ace18eae18467b900a12c07f Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Tue, 12 May 2020 16:25:31 -0700 Subject: soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size() This change uses cpu_phys_address_size() to calculate the size of high MMIO region instead of a macro for each SoC. This ensures that the entire range above TOUUD that can be addressed by the CPU is used for MMIO above 4G boundary. Change-Id: I01a1a86c0c65856f9f35185c2f233c58f18f5dfe Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/41347 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/include/soc/iomap.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index a3db5c033e..d3fb9579fd 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -61,8 +61,6 @@ #define PTT_TXT_BASE_ADDRESS 0xfed30800 #define PTT_PRESENT 0x00070000 -#define ABOVE_4GB_MEM_BASE_SIZE (64ULL * GiB) - /* * I/O port address space */ -- cgit v1.2.3