From df21440d682403aec56912a44fb7c4bffd507e8e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 14 Dec 2015 16:44:26 -0600 Subject: intel/skylake: provide default VR configuration FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is non-zero. That behavior is not desired because it's not clear what the behavior will be for various processor SKUs. Instead provide default values for the VR config. Note that PSI3 and PSI4 are not enabled for those defaults. BUG=chrome-os-partner:48466 BRANCH=None TEST=Built and booted glados. Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55 Signed-off-by: Patrick Georgi Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17 Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/318263 Original-Reviewed-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/12983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/chip.c | 24 +----- src/soc/intel/skylake/include/soc/vr_config.h | 7 ++ src/soc/intel/skylake/vr_config.c | 107 ++++++++++++++++++++++++++ 4 files changed, 117 insertions(+), 22 deletions(-) create mode 100644 src/soc/intel/skylake/vr_config.c (limited to 'src/soc/intel/skylake') diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 9c578c56c1..32076e74ab 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -58,6 +58,7 @@ ramstage-y += systemagent.c ramstage-y += tsc_freq.c ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c +ramstage-y += vr_config.c ramstage-y += xhci.c smm-y += cpu_info.c diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f4dc4a729f..b6485f7d94 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -359,28 +359,8 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) else params->PsfUnlock = 0; - for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) { - params->VrConfigEnable[i] = - config->domain_vr_config[i].vr_config_enable; - params->Psi1Threshold[i] = - config->domain_vr_config[i].psi1threshold; - params->Psi2Threshold[i] = - config->domain_vr_config[i].psi2threshold; - params->Psi3Threshold[i] = - config->domain_vr_config[i].psi3threshold; - params->Psi3Enable[i] = - config->domain_vr_config[i].psi3enable; - params->Psi4Enable[i] = - config->domain_vr_config[i].psi4enable; - params->ImonSlope[i] = - config->domain_vr_config[i].imon_slope; - params->ImonOffset[i] = - config->domain_vr_config[i].imon_offset; - params->IccMax[i] = - config->domain_vr_config[i].icc_max; - params->VrVoltageLimit[i] = - config->domain_vr_config[i].voltage_limit; - } + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ dev = dev_find_slot(0, PCH_DEVFN_SPI); diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 926ddf1a16..204b848a57 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -23,6 +23,8 @@ #ifndef _SOC_VR_CONFIG_H_ #define _SOC_VR_CONFIG_H_ +#include + struct vr_config { /* @@ -61,6 +63,8 @@ struct vr_config { int voltage_limit; }; +#define VR_CFG_AMP(i) ((i) * 4) + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced @@ -74,4 +78,7 @@ enum vr_domain{ NUM_VR_DOMAINS }; +void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain, + const struct vr_config *cfg); + #endif diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c new file mode 100644 index 0000000000..40223e32cd --- /dev/null +++ b/src/soc/intel/skylake/vr_config.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include + +/* Default values for domain configuration. PSI3 and PSI4 are disabled. */ +static const struct vr_config default_configs[NUM_VR_DOMAINS] = { + [VR_SYSTEM_AGENT] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + }, + [VR_IA_CORE] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }, + [VR_RING] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + }, + [VR_GT_UNSLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }, + [VR_GT_SLICED] = { + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + }, +}; + +void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain, + const struct vr_config *chip_cfg) +{ + const struct vr_config *cfg; + + if (domain < 0 || domain >= NUM_VR_DOMAINS) + return; + + /* Use device tree override if requested. */ + if (chip_cfg->vr_config_enable) + cfg = chip_cfg; + else + cfg = &default_configs[domain]; + + params->VrConfigEnable[domain] = cfg->vr_config_enable; + params->Psi1Threshold[domain] = cfg->psi1threshold; + params->Psi2Threshold[domain] = cfg->psi2threshold; + params->Psi3Threshold[domain] = cfg->psi3threshold; + params->Psi3Enable[domain] = cfg->psi3enable; + params->Psi4Enable[domain] = cfg->psi4enable; + params->ImonSlope[domain] = cfg->imon_slope; + params->ImonOffset[domain] = cfg->imon_offset; + params->IccMax[domain] = cfg->icc_max; + params->VrVoltageLimit[domain] = cfg->voltage_limit; +} -- cgit v1.2.3