From 2fd49721b17f9020c2b449aad778f011dae7bf46 Mon Sep 17 00:00:00 2001
From: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Date: Mon, 16 Dec 2019 23:41:36 -0800
Subject: soc/intel/tigerlake: Update chip files

Update chip files to include :
  - Update chip.c based on TGL FSP
  - Update chip.h based on TGL FSP
  - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update
  - Update pmc_utils.c and JSL devicetree for build failure

Reference
PCH EDS#576591 vol1 rev1.2

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/tigerlake/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/soc/intel/tigerlake/Kconfig')

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index f1ae8a82c9..9340f6980c 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -115,6 +115,11 @@ config MAX_ROOT_PORTS
 	default 16 if SOC_INTEL_JASPERLAKE
 	default 12 if SOC_INTEL_TIGERLAKE
 
+config MAX_PCIE_CLOCKS
+	int
+	default 7 if SOC_INTEL_TIGERLAKE
+	default 16 if SOC_INTEL_JASPERLAKE
+
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000
-- 
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