From 32b8a51153f7836b841cb2da832e9e78b32e1227 Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Tue, 31 Mar 2020 22:56:13 -0700 Subject: soc/intel/tigerlake: Control SATA and DMI power optimization FSP provides the UPD's for SATA and DMI power optimization. In this patch we are adding the soc's config support to set those power optimization bits in FSP. By default those optimizations are enabled. To disable those we need to set the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1 in devicetree. BUG=b:151162424 BRANCH=None TEST=Build and boot volteer and TGL RVP. Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749 Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/tigerlake/fsp_params.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/intel/tigerlake/fsp_params.c') diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 11d79529ed..73c41c8519 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -184,6 +184,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* + * Power Optimizer for DMI and SATA. + * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. + * Boards not needing the optimizers explicitly disables them by setting + * these disable variables to 1 in devicetree overrides. + */ + params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); + params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) -- cgit v1.2.3