From c96f802f7f126dadc41c95a8b63e9dec85cbbfde Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 3 Mar 2020 20:31:58 +0100 Subject: intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add registers that are relevant for the case intrusion detection functionality. Intel documents: 332691-003EN, 335193-006, 341081-001, ... Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/tigerlake/include/soc/smbus.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/intel/tigerlake/include') diff --git a/src/soc/intel/tigerlake/include/soc/smbus.h b/src/soc/intel/tigerlake/include/soc/smbus.h index 50ea044e53..0ad565a613 100644 --- a/src/soc/intel/tigerlake/include/soc/smbus.h +++ b/src/soc/intel/tigerlake/include/soc/smbus.h @@ -29,9 +29,14 @@ #define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 #define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) /* * Default slave address value for PCH. This value is set to match default -- cgit v1.2.3