From 0cc63ccaa26c21d02025f3b1c31f2fc4e8adc697 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 5 Aug 2020 14:45:58 -0700 Subject: soc/intel/tigerlake: add common routine for DDR init Add a common routine meminit_ddr() that calls the appropriate meminit routine based on whether the memory type requested is LPDDR4x or DDR4. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation. I do not have a DDR4 board to test this on. Change-Id: Ib2039eb89211efc48d10897eb679d05f567ae5a1 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/44249 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Ravishankar Sarawadi Reviewed-by: Duncan Laurie --- src/soc/intel/tigerlake/meminit.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/soc/intel/tigerlake/meminit.c') diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 790e2e0499..0c6f0b0f88 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -435,3 +435,20 @@ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, } } } + +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated) +{ + switch (board_cfg->mem_type) { + case MEMTYPE_DDR4: + meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, + half_populated); + break; + case MEMTYPE_LPDDR4X: + meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, + half_populated); + break; + default: + die("Unsupported memory type = %d!\n", board_cfg->mem_type); + } +} -- cgit v1.2.3