From d2132469ae86d7287576a2ba3211cdbfeb572703 Mon Sep 17 00:00:00 2001 From: Sumeet R Pawnikar Date: Fri, 15 May 2020 15:55:37 +0530 Subject: tigerlake: update processor power limits configuration Update processor power limit configuration parameters based on common code base support for Intel Tigerlake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on volteer system Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd Signed-off-by: Sumeet R Pawnikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345 Reviewed-by: Wonkyu Kim Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/systemagent.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel/tigerlake/systemagent.c') diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 4cdca50410..977c6674e7 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -7,10 +7,13 @@ */ #include +#include #include #include +#include #include #include +#include #include /* @@ -60,9 +63,18 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index) */ void soc_systemagent_init(struct device *dev) { + struct soc_power_limits_config *soc_config; + config_t *config; + /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); /* Enable BIOS Reset CPL */ enable_bios_reset_cpl(); + + /* Configure turbo power limits 1ms after reset complete bit */ + mdelay(1); + config = config_of_soc(); + soc_config = &config->power_limits_config; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); } -- cgit v1.2.3