From de2ab41fc43152b652af7c1f658b1c27926afd6c Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 11 Jan 2021 16:14:14 +0800 Subject: soc/intel/common: Move L1_substates_control to pcie_rp.h L1_substates_control is common define. Move out of soc level. Signed-off-by: Eric Lai Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/chip.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/soc/intel/tigerlake') diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 86e77da972..d3062cc720 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -247,12 +248,7 @@ struct soc_intel_tigerlake_config { uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; -- cgit v1.2.3