From ebb7f54b1a107816e4f83bc31f1631acb85700d1 Mon Sep 17 00:00:00 2001
From: Johnny Lin <johnny_lin@wiwynn.com>
Date: Wed, 19 Feb 2020 15:52:45 +0800
Subject: soc/intel/xeon_sp: Enable LPC generic IO decode range

To use Intel common block LPC function that enables the IO ranges
defined in devicetree.cb.

Tested on OCP Tioga Pass with BMC LPC working.

Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38994
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/xeon_sp/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/intel/xeon_sp/Makefile.inc')

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 3178a4e2bf..59350bf967 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -24,6 +24,7 @@ subdirs-y += ../../../cpu/x86/cache
 subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
 
 bootblock-y += bootblock/bootblock.c
+bootblock-y += lpc.c
 bootblock-y += spi.c
 
 postcar-y += soc_util.c
-- 
cgit v1.2.3