From 641642e11ce9a7e9509a54cb1e917ed89b965e3d Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Tue, 26 May 2020 13:42:28 -0700 Subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release Update Cooperlake-SP (CPX-SP) FSP header files to WW20 release. As CPX-SP FSP engineering is on-going (the processor Mass Production is some time in this year). These header files will be adjusted when changes are necessary with newer FSP release. This commit corresponds to FSP release WW20 (tag WHITLEY.0.PRB.0016.D.65). Also update soc/xeon_sp code file and Skylake-SP header file accordingly to use FsptPort80RouteDisable instead of PcdPort80RouteDisable. Signed-off-by: Jonathan Zhang Signed-off-by: Johnny Lin Signed-off-by: Reddy Chagam Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/40034 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/soc/intel/xeon_sp/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/xeon_sp/bootblock.c') diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 72d9742af8..f6653e2034 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -25,7 +25,7 @@ const FSPT_UPD temp_ram_init_params = { .Reserved1 = {0}, }, .FsptConfig = { - .PcdFsptPort80RouteDisable = 0, + .FsptPort80RouteDisable = 0, .ReservedTempRamInitUpd = {0}, }, .UnusedUpdSpace0 = {0}, -- cgit v1.2.3