From c62c98a884231ef36bf3eb613b2d24e37c89c4d2 Mon Sep 17 00:00:00 2001
From: Rocky Phagura <rphagura@fb.com>
Date: Sat, 23 May 2020 20:29:00 -0700
Subject: soc/intel/xeon_sp: Early programming of ACPI bar

ACPI bar was not programmed previously for which is needed to enable SMI's and
to check SMI status registers. The architecture of Lewisburg PCH is very
similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.

TEST=build for Tiogapass and check ACPI base. Log message will now show
pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing
to io port 0x500.

Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
---
 src/soc/intel/xeon_sp/bootblock.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/soc/intel/xeon_sp/bootblock.c')

diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
index 7f14be6329..72d9742af8 100644
--- a/src/soc/intel/xeon_sp/bootblock.c
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -9,6 +9,7 @@
 #include <cpu/x86/mtrr.h>
 #include <intelblocks/lpc_lib.h>
 #include <soc/pci_devs.h>
+#include <soc/bootblock.h>
 
 const FSPT_UPD temp_ram_init_params = {
 	.FspUpdHeader = {
@@ -53,4 +54,5 @@ void bootblock_soc_init(void)
 {
 	if (CONFIG(BOOTBLOCK_CONSOLE))
 		printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
+	bootblock_pch_init();
 }
-- 
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