From decf7dc4f80d6b19798cd0cd6f0be794bd9463bb Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Mon, 27 Jul 2020 15:26:30 -0700 Subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE CPX-SP processor has 2 IMC, there are 3 channels per IMC, 2 DIMMs per channel. It supports DDR4. Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly. Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a Signed-off-by: Jonathan Zhang Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/Kconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/soc/intel/xeon_sp/cpx') diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 9c6450e73c..bd1fa97239 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -68,4 +68,15 @@ config SOC_INTEL_COMMON_BLOCK_P2SB select CACHE_MRC_SETTINGS +# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel +# Default value is set to one socket, full config. +config DIMM_MAX + int + default 12 + +# DDR4 +config DIMM_SPD_SIZE + int + default 512 + endif -- cgit v1.2.3