From 7919d618f8ffd742df1e5d4804656b20412f4999 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 2 Apr 2020 17:27:54 -0700 Subject: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration Add PCIe enumeration and resource assignment/allocation. Xeon-SP processor family has split IIO design, where PCIe domain 0 is split into multiple stacks. Each stack has its own resource ranges (eg. IO resource, mem32 resource, mem64 resource). The stack itself is not PCIe device, it does not have config space to be probed/programmed. The stack is programmed by FSP. coreboot needs to take into account of stack when doing PCIe enumeration and resource allocation. Current coreboot PCIe resource allocator does not support the concept of split IIO stack, thus entire support is done locally in this patch. In near future, improvements will be done, first generalize for xeon-sp, then generalize for coreboot PCIe device code. Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40110 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Philipp Deppenwiese --- src/soc/intel/xeon_sp/include/soc/util.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/xeon_sp/include') diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 24baca6eb7..159efeba2c 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -4,6 +4,7 @@ #define _XEON_SP_SOC_UTIL_H_ #include +#include void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3); void unlock_pam_regions(void); -- cgit v1.2.3