From e07ea4cd38c5c232515a8755d2b4fbff6f12b949 Mon Sep 17 00:00:00 2001 From: Jingle Hsu Date: Wed, 1 Jul 2020 18:26:49 +0800 Subject: soc/intel/xeon_sp: Add RTC failure checking Add a weak function mainboard_rtc_failed() for mainboard customization. Check RTC_PWR_STS bit for RTC battery removal or CMOS clear jumper triggered event. Signed-off-by: Jingle Hsu Change-Id: Ic6da84277e71a5c51dfa4d97d5d0c0184478e8f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43004 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/include/soc/pmc.h | 2 +- src/soc/intel/xeon_sp/include/soc/romstage.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/xeon_sp/include') diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index d3bad1b715..49e58d366a 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -25,6 +25,6 @@ #define GEN_PMCON_B 0xa4 #define SLP_STR_POL_LOCK (1 << 18) #define ACPI_BASE_LOCK (1 << 17) - +#define RTC_BATTERY_DEAD (1 << 2) #endif diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index 42425e29d0..8bd5709fe0 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -8,5 +8,6 @@ /* These functions are weak and can be overridden by a mainboard functions. */ void mainboard_memory_init_params(FSPM_UPD * mupd); +void mainboard_rtc_failed(void); #endif /* _SOC_ROMSTAGE_H_ */ -- cgit v1.2.3