From d5f24dd99bb245a6de2d8ca86bfabda05bdb82d1 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Fri, 21 Aug 2020 13:32:20 -0700 Subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc Intel CPX-SP FSP ww34 release added some features: a. change DDR frequency limit. b. define MRC debug message verbosity level. c. enable/disablee of PCH DCI. In addition, there are some changes to HOB data structures. Update UPD and HOB header files and adapt soc accordingly. TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay. Signed-off-by: Jonathan Zhang Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Christian Walter Reviewed-by: Johnny Lin Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/cpx/hob_display.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/xeon_sp') diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c index 3d61a8209c..12c6feb398 100644 --- a/src/soc/intel/xeon_sp/cpx/hob_display.c +++ b/src/soc/intel/xeon_sp/cpx/hob_display.c @@ -133,22 +133,16 @@ static void soc_display_iio_universal_data_hob(const IIO_UDS *hob) printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality); printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase); printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit); - printk(BIOS_DEBUG, "\t\tIoBase: 0x%x\n", ri->IoBase); - printk(BIOS_DEBUG, "\t\tIoLimit: 0x%x\n", ri->IoLimit); + printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", + ri->PciResourceIoBase); + printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", + ri->PciResourceIoLimit); printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase); printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit); printk(BIOS_DEBUG, "\t\tMmio32Base: 0x%x\n", ri->Mmio32Base); printk(BIOS_DEBUG, "\t\tMmio32Limit: 0x%x\n", ri->Mmio32Limit); printk(BIOS_DEBUG, "\t\tMmio64Base: 0x%llx\n", ri->Mmio64Base); printk(BIOS_DEBUG, "\t\tMmio64Limit: 0x%llx\n", ri->Mmio64Limit); - printk(BIOS_DEBUG, "\t\tPciResourceBusBase: 0x%x\n", - ri->PciResourceBusBase); - printk(BIOS_DEBUG, "\t\tPciResourceBusLimit: 0x%x\n", - ri->PciResourceBusLimit); - printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n", - ri->PciResourceIoBase); - printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n", - ri->PciResourceIoLimit); printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n", ri->PciResourceMem32Base); printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n", -- cgit v1.2.3