From 03abf8dbd16fa10a513c8d6dc831315b9cc73144 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 14 Mar 2020 13:19:14 +0530 Subject: soc/intel/Kconfig: Avoid specifying dedicated chipset name This patch ensures all IA chipsets and common Kconfig files are getting included without specifying dedicated chipset names. TEST=Able to compile CML and TGL RVP. Change-Id: Ic2d8a8ac1c4acfabd4ded1bfd4ff359e820e174b Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/39530 Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Aamir Bohra Tested-by: build bot (Jenkins) --- src/soc/intel/Kconfig | 14 ++------ src/soc/intel/common/Kconfig | 71 ------------------------------------- src/soc/intel/common/Kconfig.common | 71 +++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+), 83 deletions(-) delete mode 100644 src/soc/intel/common/Kconfig create mode 100644 src/soc/intel/common/Kconfig.common (limited to 'src/soc/intel') diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 47efc4d18f..d5190683ae 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -1,18 +1,8 @@ # Load all chipsets -source "src/soc/intel/apollolake/Kconfig" -source "src/soc/intel/baytrail/Kconfig" -source "src/soc/intel/braswell/Kconfig" -source "src/soc/intel/broadwell/Kconfig" -source "src/soc/intel/cannonlake/Kconfig" -source "src/soc/intel/denverton_ns/Kconfig" -source "src/soc/intel/quark/Kconfig" -source "src/soc/intel/skylake/Kconfig" -source "src/soc/intel/icelake/Kconfig" -source "src/soc/intel/tigerlake/Kconfig" -source "src/soc/intel/xeon_sp/Kconfig" +source "src/soc/intel/*/Kconfig" # Load common config -source "src/soc/intel/common/Kconfig" +source "src/soc/intel/common/Kconfig.common" config INTEL_HAS_TOP_SWAP bool diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig deleted file mode 100644 index 44c2392abc..0000000000 --- a/src/soc/intel/common/Kconfig +++ /dev/null @@ -1,71 +0,0 @@ -config SOC_INTEL_COMMON - bool - select HAVE_DISPLAY_MTRRS - help - common code for Intel SOCs - -if SOC_INTEL_COMMON - -comment "Intel SoC Common Code" -source "src/soc/intel/common/block/Kconfig" - -comment "Intel SoC Common PCH Code" -source "src/soc/intel/common/pch/Kconfig" - -comment "Intel SoC Common coreboot stages" -source "src/soc/intel/common/basecode/Kconfig" - -config SOC_INTEL_COMMON_RESET - bool - default n - select HAVE_CF9_RESET - -config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - bool - default n - -config ACPI_CONSOLE - bool - default n - help - Provide a mechanism for serial console based ACPI debug. - -config MMA - bool "Enable MMA (Memory Margin Analysis) support for Intel Core" - default n - depends on SOC_INTEL_KABYLAKE || SOC_INTEL_SKYLAKE - help - Set this option to y to enable MMA (Memory Margin Analysis) support - -config MMA_BLOBS_PATH - string "Path to MMA blobs" - depends on MMA - default "3rdparty/blobs/soc/intel/kabylake/mma-blobs" if SOC_INTEL_KABYLAKE - default "3rdparty/blobs/soc/intel/skylake/mma-blobs" if SOC_INTEL_SKYLAKE - -config SOC_INTEL_COMMON_ACPI - bool - default n - -config SOC_INTEL_COMMON_NHLT - bool - default n - -config TPM_TIS_ACPI_INTERRUPT - int - help - acpi_get_gpe() is used to provide interrupt status to TPM layer. - This option specifies the GPE number. - -config SOC_INTEL_DEBUG_CONSENT - bool "Enable SOC debug interface" - default n - help - Set this option to enable default debug interface of SoC such as DBC - or DCI. - -config SMM_MODULE_STACK_SIZE - hex - default 0x800 - -endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common new file mode 100644 index 0000000000..44c2392abc --- /dev/null +++ b/src/soc/intel/common/Kconfig.common @@ -0,0 +1,71 @@ +config SOC_INTEL_COMMON + bool + select HAVE_DISPLAY_MTRRS + help + common code for Intel SOCs + +if SOC_INTEL_COMMON + +comment "Intel SoC Common Code" +source "src/soc/intel/common/block/Kconfig" + +comment "Intel SoC Common PCH Code" +source "src/soc/intel/common/pch/Kconfig" + +comment "Intel SoC Common coreboot stages" +source "src/soc/intel/common/basecode/Kconfig" + +config SOC_INTEL_COMMON_RESET + bool + default n + select HAVE_CF9_RESET + +config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + bool + default n + +config ACPI_CONSOLE + bool + default n + help + Provide a mechanism for serial console based ACPI debug. + +config MMA + bool "Enable MMA (Memory Margin Analysis) support for Intel Core" + default n + depends on SOC_INTEL_KABYLAKE || SOC_INTEL_SKYLAKE + help + Set this option to y to enable MMA (Memory Margin Analysis) support + +config MMA_BLOBS_PATH + string "Path to MMA blobs" + depends on MMA + default "3rdparty/blobs/soc/intel/kabylake/mma-blobs" if SOC_INTEL_KABYLAKE + default "3rdparty/blobs/soc/intel/skylake/mma-blobs" if SOC_INTEL_SKYLAKE + +config SOC_INTEL_COMMON_ACPI + bool + default n + +config SOC_INTEL_COMMON_NHLT + bool + default n + +config TPM_TIS_ACPI_INTERRUPT + int + help + acpi_get_gpe() is used to provide interrupt status to TPM layer. + This option specifies the GPE number. + +config SOC_INTEL_DEBUG_CONSENT + bool "Enable SOC debug interface" + default n + help + Set this option to enable default debug interface of SoC such as DBC + or DCI. + +config SMM_MODULE_STACK_SIZE + hex + default 0x800 + +endif # SOC_INTEL_COMMON -- cgit v1.2.3