From 503d3247e48d803ce36e98d2064cf22220bb0dfd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 5 Mar 2019 07:54:28 +0200 Subject: Remove DEFAULT_PCIEXBAR alias MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber --- src/soc/intel/denverton_ns/acpi/northcluster.asl | 2 +- src/soc/intel/denverton_ns/include/soc/iomap.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/soc/intel') diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index bbfa13313a..f212557a56 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -138,7 +138,7 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { // PCIEXBAR memory range - Memory32Fixed(ReadOnly, DEFAULT_PCIEXBAR, 0x10000000) + Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) // TSEG Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB) }) diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index a7548d40a3..8bcef91c2e 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -23,7 +23,6 @@ */ /* Northbridge BARs */ -#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */ #define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ /* Southbridge internal device IO BARs (Set to match FSP settings) */ -- cgit v1.2.3