From 6390c5070363d834443ecdfb6b77c077fc2576dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 9 Jan 2019 06:37:24 +0200 Subject: soc/intel/denverton_ns: Fix missing tsc_freq_mhz() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It was relying on bad weak implementation for postcar and verstage. Change-Id: I5a520e0166198c0565349c164f143f4a43649861 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/30763 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: David Guckian Reviewed-by: Nico Huber Reviewed-by: Vanny E --- src/soc/intel/denverton_ns/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index c024c3af67..e9d5022511 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -31,6 +31,7 @@ bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c postcar-y += memmap.c postcar-y += spi.c +postcar-y += tsc_freq.c postcar-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c romstage-y += memmap.c @@ -80,6 +81,7 @@ smm-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c verstage-y += memmap.c verstage-y += reset.c verstage-y += spi.c +verstage-y += tsc_freq.c verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include -- cgit v1.2.3