From 6d7063c2ac562cab72e9556102da87c61be32d3f Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 29 Aug 2017 17:26:48 -0700 Subject: soc/intel/cannonlake: Add Vboot/ChromeOS support Add Vboot and ChromeOS support in SOC Kconfig, include a separated verstage in Makefiles.inc as well. Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Kconfig | 11 +++++++++++ src/soc/intel/cannonlake/Makefile.inc | 2 ++ 2 files changed, 13 insertions(+) (limited to 'src/soc/intel') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f72c2b302a..9525ab488d 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -123,4 +123,15 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex default 0xc35 +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + endif diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index dba04a85fa..d3fd5f2e8c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -45,7 +45,9 @@ postcar-y += spi.c postcar-$(CONFIG_UART_DEBUG) += uart.c verstage-y += gspi.c +verstage-y += pmutil.c verstage-y += spi.c +verstage-$(CONFIG_UART_DEBUG) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake -- cgit v1.2.3